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ltc1704/ltc1704b 1 1704bfa descriptio u features applicatio s u typical applicatio u the ltc ? 1704/ltc1704b include a high power synchro- nous switching regulator controller plus a linear regulator controller. the switching regulator controller is designed to drive a pair of n-channel mosfets in a voltage mode, synchronous buck configuration to provide the main sup- ply. the constant frequency, true pwm architecture switches at 550khz, minimizing external component size, cost and optimizing load transient performance. the ltc1704 features automatic transition to power saving burst mode operation at light loads. the ltc1704b does not shift into burst mode operation at light loads, eliminat- ing low frequency output ripple at the expense of light load efficiency. the linear regulator controller is designed to drive an external npn power transistor to provide up to 2a of current to an auxiliary load. the ltc1704/ltc1704b deliver better than 1.5% dc accuracy at the switcher outputs and 2% at the linear regulator outputs. high performance feedback loops allow the circuit to keep total output regulation within 5% under all transient conditions. an open-drain pgood output indicates when both outputs are within 10% of their regulated values. n multiple logic supply generator n distributed power applications n high efficiency power conversion , ltc and lt are registered trademarks of linear technology corporation. n dual regulated outputs: one switching regulator and one linear regulator n excellent dc accuracy: 1.5% for switcher and 2% for linear regulator n external n-channel mosfet architecture n no external current sense resistor required n burst mode ? operation at light load (ltc1704) n continuous switching at light load (ltc1704b) n linear regulator with programmable current limit n linear regulator with programmable start-up delay n low shutdown current: <150 m a n high efficiency over wide load current range n pgood flag monitors both outputs n small 16-pin narrow ssop package 550khz synchronous switching regulator controller plus linear regulator controller burst mode is a registered trademark of linear technology corporation. 5v to 1.8v/15a and 1.5v/2a application boost tg sw pgood regilm c cp 1 f 10 13.7k 11k 1.8k 10k 8.06k 1800pf 5k 470k 10 f 10 f mbr0520lt1 16 1 2 qtb 1 f l1 0.68 h 11 12 10 0.1 f 1000pf on semi d44h11 698 806 run/ss 4 gnd 8 regdr 7 regfb 9 1704 ta01 pv cc ltc1704 v cc qta bg 14 i max 3 pgnd 13 comp 5 fb 6 qba qbb + 100 f tant v outreg 1.5v 2a v outsw 330pf 1800pf c in : kemet t510x337k010as c outsw : panasonic eefue0g181r l: sumida cep125-4712-t007 qta, qtb, qba, qbb: fairchild fds6670a + + c outsw 180 f 4v 6 c in 330 f 10v 3 v in 5v v outsw 1.8v 15a + + 15 i load (a) 0 efficiency (%) 80 90 100 12 1704 g04 70 60 50 3 6 9 15 v in = 5v v outsw = 1.8v t a = 25 c qt = qb = 2xfds6670a switcher efficiency
ltc1704/ltc1704b 2 1704bfa supply voltage v cc , pv cc .............................................................. 6v boost ................................................................. 12v boost C sw ......................................................... 6v input voltage sw ............................................................. C1v to 6v fb, regfb, regilm, run/ss, i max .......................... C 0.3v to (v cc + 0.3v) peak output current <10 m s tg, bg (note 7) ..................................................... 5a operating temperature range (note 2) .. C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number t jmax = 125 c, q ja = 130 c/w consult ltc marketing for parts specified with wider operating temperature ranges. ltc1704egn LTC1704BEGN absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = pv cc = boost = 5v, unless otherwise specified. (note 3) (note 1) gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 tg sw i max run/ss comp fb regdr gnd boost pv cc bg pgnd pgood v cc regilm regfb symbol parameter conditions min typ max units v cc v cc supply voltage l 3.15 5 5.5 v pv cc pv cc supply voltage (note 4) l 3.15 5 5.5 v bv cc boost pin voltage v boost C v sw (note 4) l 3.15 5 5.5 v i vcc v cc supply current test circuit l 4.5 8 ma v run/ss = 0v, v regilm = 0v l 75 150 m a i pvcc pv cc supply current test circuit, no load at drivers l 36 ma v run/ss = 0v (notes 5, 6) l 50 m a i boost boost pin current test circuit l 26 ma v run/ss = 0v (notes 5, 6) l 50 m a v shdn run/ss shutdown threshold v run/ss - l 0.2 0.5 v i ss run/ss source current v run/ss = 0v C 3 m a switcher control loop v fb feedback voltage l 0.788 0.800 0.812 v i fb feedback input current l 1 m a dv fb feedback voltage line regulation v cc = 3.3v to 5.5v l 0.01 0.1 %/v output voltage load regulation (note 7) l C 0.2 C 0.1 % a fb feedback amplifier dc gain l 74 85 db gbw feedback amplifier gain bandwidth product f = 100khz (note 7) 20 mhz i comp feedback amplifier output sink/source current l 3 10 ma v pgood negative power good threshold l C15 C10 C6 % positive power good threshold l 61015 % i imax i max source current v imax = 0v l C11.5 C10 C 8.5 m a gn part marking 1704 1704b
ltc1704/ltc1704b 3 1704bfa electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = pv cc = boost = 5v, unless otherwise specified. (note 3) note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the ltc1704e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. note 4: pv cc and bv cc (v boost C v sw ) must be greater than v gs(on) of the external mosfets to ensure proper operation. note 5: supply current in normal operation is dominated by the current needed to charge and discharge the external mosfet gates. this current will vary with supply voltage and the external mosfets used. note 6: supply current in shutdown is dominated by external mosfet leakage and may be significantly higher than the quiescent current drawn by the ltc1704, especially at elevated temperature. note 7: guaranteed by design, not subject to test. note 8: rise and fall times are measured using 10% and 90% levels. delay and nonoverlap times are measured using 50% levels. note 9: dropout voltage is the minimum v cc to v regdr voltage differential required to maintain regulation at the specified driver output current. symbol parameter conditions min typ max units switcher switching characteristics f osc oscillator frequency test circuit l 460 550 650 khz dc max maximum duty cycle l 87 90 93 % t nov driver nonoverlap test circuit (note 8) l 10 25 120 ns t r , t f driver rise/fall time test circuit (note 8) l 15 100 ns linear regulator controller v regfb feedback voltage test circuit, r regilm = 680k 0.784 0.800 0.816 v l 0.780 0.800 0.820 v i regfb regfb input current l 1 m a dv regfb feedback voltage line regulation test circuit, v cc = 4.5v to 5.5v l 0.05 0.2 %/v feedback voltage load regulation test circuit, i regdr = 0ma to 30ma l C0.2 C0.05 % i regdr driver output current test circuit l 30 ma r regilm = 680k, v regfb = 0.76v, v regdr = 3.3v 20 ma r regilm = 680k, v regfb = 0v, v regdr = 1v 6 ma v dropout driver dropout voltage test circuit, i regdr = 30ma, v regdr = 3.3v, l 0.65 1.1 v dv regfb = C1% (note 9) v regilm regilm threshold test circuit, r regilm = 680k 0.8 v i regilmint regilm internal pull-up current v regilm = 0v C1.9 m a v pgood negative regfb power good threshold l C15 C10 C6 % positive regfb power good threshold l 61015 % pgood i pgood v pgood sink current power good l 10 m a power bad l 10 ma v olpg v pgood output low voltage i pgood = 1ma l 0.03 0.1 v t pgood v pgood falling edge delay (note 8) l 0.5 1 4 m s v pgood rising edge delay (note 8) l 10 20 40 m s
ltc1704/ltc1704b 4 1704bfa typical perfor a ce characteristics uw temperature ( c) ?0 v fb (v) 0.804 0.808 0.812 25 75 1704 g01 0.800 0.796 ?5 0 50 100 125 0.792 0.788 v cc = 5v v cc (v) 3 0.80 ? v fb (mv) ? v fb (%) 0.48 0.16 0.16 3.5 4 4.5 5 1704 g02 5.5 0.48 0.80 0.64 0.32 0 0.32 0.64 0.10 0.06 0.02 0.02 0.06 0.10 0.08 0.04 0 0.04 0.08 6 t a = 25 c i load (a) 0 ?.6 0 0.6 12 1704 g03 ?.2 ?.8 369 15 ?.4 ?.0 ?.6 0.03 0.03 0 0.07 0.10 0.13 0.17 0.20 ? v outsw (mv) ? v outsw (%) t a = 25 c v outsw = 1.8v v fb line regulation v outsw 0.5a to 5.5a load step (burst mode operation) v outsw load regulation 100 m s/div 1704 g05 ch1: v outsw = 1.8v, ac 50mv/div ch2: 0.5a to 5.5a load, 5a div v outsw 5a to 10a load step 50 m s/div 1704 g06 ch1: v outsw = 1.8v, ac 50mv/div ch2: 5a to 10a load, 5a div 20 m s/div 1704 g07 ch1: v outsw = 1.8v, ac 20mv/div ch2: v tg , 5v div v outsw burst mode operation at 1a load temperature ( c) ?0 18 20 24 25 75 1704 g08 16 14 ?5 0 50 100 125 12 10 22 current limit threshold (a) v in = 5v v outsw = 1.8v ? v outsw = ?% r imax = 13.7k qt = qb = 2xfds6670a switcher current limit threshold vs temperature v fb vs temperature
ltc1704/ltc1704b 5 1704bfa typical perfor a ce characteristics uw v outsw vs load current load current (a) 0 v outsw (v) 1.0 1.5 16 1704 g09 0.5 0 4 8 12 20 2.0 v in = 5v v outsw = 1.8v t a = 25 c r imax = 13.7k qt = qb = 2xfds6670a temperature ( c) ?0 i imax ( a) 9.5 9.0 8.5 25 75 1704 g10 ?0.0 ?0.5 ?5 0 50 100 125 ?1.0 ?1.5 v cc = 5v v cc (v) 3 ?1.5 i imax ( a) ?1.0 ?0.5 ?0.0 9.5 8.5 3.5 4 4.5 5 1704 g11 5.5 6 9.0 t a = 25 c i imax vs temperature i imax vs v cc f osc vs temperature temperature ( c) ?0 460 f osc (khz) 480 520 540 560 50 640 1704 g12 500 0 ?5 75 100 25 125 580 600 620 v cc = 5v f osc vs v cc v cc (v) 3 450 f osc (khz) 490 530 570 610 650 3.5 4 4.5 5 1704 g13 5.5 6 t a = 25 c maximum tg duty cycle vs temperature temperature ( c) ?0 dc max (%) 91 92 93 25 75 1704 g10 90 89 ?5 0 50 100 125 88 87 v cc = 5v tg, bg float drivers rise and fall time vs load tg, bg load (pf) 0 t r , t f (ns) 60 80 100 8000 1704 g15 40 20 50 70 90 30 10 0 2000 4000 6000 10000 t a = 25 c pv cc = boost = 5v v regfb vs temperature temperature ( c) ?0 v regfb (v) 0.815 25 ltxxx ?tpcxx 0.800 0.790 ?5 0 50 0.785 0.780 0.820 0.810 0.805 0.795 75 100 125 v regdr = 3.3v v regfb line regulation v cc (v) 3 ? v regfb (mv) ? v regfb (%) 0.4 0 0.4 4.5 5.5 1704 g17 0.8 ?.2 ?.6 3.5 4 5 0.8 1.2 1.6 0.05 0 0.05 0.10 0.15 0.20 0.10 0.15 0.20 6 t a = 25 c v regdr = 0.8v
ltc1704/ltc1704b 6 1704bfa typical perfor a ce characteristics uw v outreg load regulation linear regulator dropout voltage vs temperature i outreg (a) 0 ?.5 0 0.5 1.6 1704 g18 ?.0 ?.5 0.4 0.8 1.2 2 ?.0 ?.5 ?.0 0.03 0.03 0 0.07 0.10 0.13 0.17 0.20 ? v outreg (mv) ? v outreg (%) t a = 25 c v outreg = 1.5v i regilm = 9 a qext = d44h11 temperature ( c) ?0 v dropout (v) 1.0 25 1704 g19 0.7 0.5 ?5 0 50 0.4 0.3 1.1 0.9 0.8 0.6 75 100 125 i regdr = 30ma v regdr = 3.3v v outreg 0.1a to 2.1a load step 50 m s/div 1704 g20 ch1: v outreg = 1.5v, ac 50mv/div ch2: 0.1a to 2.1a load, 1a div minimum v cc vs v outreg v outreg (v) 0.9 3.0 minimum v cc (v) 3.5 4.0 4.5 5.0 5.5 1.3 1.7 2.1 2.5 1704 g21 2.9 3.3 i regilm = 9 a i outreg = 2a ? v outreg = ?% qext = d44h11 t a = 40 c t a = 25 c c delay (pf) 0 start-up time ( s) 300 900 1000 1100 6000 8000 1704 g22 100 700 500 200 800 0 600 400 2000 4000 10000 t a = 25 c v outreg = 1.5v i regilm = 6.2 a i regilm = 9 a i regilm ( a) 0 35 30 25 20 15 10 5 0 610 1704 g23 24 812 i regdr (ma) linear regulator start-up time vs c delay i regdr vs i regilm linear regulator current limit threshold vs temperature temperature ( c) ?0 1.0 current limit threshold (a) 1.5 2.0 2.5 3.0 25 0 25 50 1704 g24 75 100 125 v inreg = 1.8v v outreg = 1.5v i regilm = 9 a qext = d44h11 i outreg (a) 0 0 v outreg (v) 0.5 1.0 1.5 2.0 0.5 1 1.5 2 1704 g25 2.5 3 t a = 25 c v inreg = 1.8v v outreg = 1.5v i regilm = 9 a qext = d44h11 v outreg vs load current v regfb (v) 0 0 i regdr (ma) 5 10 15 20 0.2 0.4 0.6 0.8 1704 g28 25 30 0.1 0.3 0.5 0.7 i regilm = 9 a i regilm = 6.2 a t a = 25 c v regdr = 0v i regdr vs v regfb v out i load
ltc1704/ltc1704b 7 1704bfa pi fu ctio s uuu tg (pin 1): switcher controller top gate drive. the tg pin drives the gate of the top n-channel mosfet, qt. the tg driver draws power from the boost pin and returns it to the sw pin, providing true floating drive to qt. tg is de- signed to typically drive up to 10,000pf of gate capacitance. sw (pin 2): switcher controller switching node. connect sw to the switching node of the main converter. the tg driver ground returns to sw, providing floating gate drive to the top n-channel mosfet, qt. the voltage at sw is compared to i max by the current limit comparator while the bottom mosfet, qb is on. the burst comparator (burst, see block diagram) monitors the potential at sw and switches to burst mode operation under light load conditions. i max (pin 3): switcher controller current limit set. the i max pin sets the current limit comparator threshold for the switcher controller. if the voltage drop across the bottom mosfet, qb, exceeds the magnitude of the volt- age at i max , the switcher controller enters current limit. the i max pin has an internal 10 m a current source pull-up, allowing the current threshold to be set with a single external resistor to pgnd. kelvin connect this current setting resistor to the source of qb. refer to the current limit programming section for more information on choos- ing r imax . run/ss (pin 4): switcher controller soft-start. a capaci- tor from run/ss to gnd controls the turn-on time and rate of rise of the switcher output voltage at power up. an internal 3 m a current source pull-up at run/ss sets the turn-on time at approximately 300ms/ m f. if both run/ss and regilm are pulled low, the ltc1704 enters shutdown mode. comp (pin 5): switcher controller loop compensation. the comp pin is connected directly to the output of the switcher controllers error amplifier and the input to the pwm comparator. use an rc network between the comp pin and the fb pin to compensate the feedback loop for optimum transient response. fb (pin 6): switcher controller feedback input. fb should be connected through a resistor divider network to v outsw to set the switcher output voltage. also, connect the switcher loop compensation network to fb. regdr (pin 7): linear regulator controller driver output. connect regdr to the base of the external npn pass transistor. the regilm pin input current controls the linear regulator controller maximum driving capability. gnd (pin 8): signal ground. all internal low power cir- cuitry returns to the gnd pin. connect to a low impedance ground, separated from the pgnd node. all feedback, typical perfor a ce characteristics uw supply current vs temperature i pvcc , i boost vs driver load temperature ( c) ?0 0 supply current (ma) 1.5 3.0 4.5 6.0 25 0 25 50 1704 g26 75 100 125 i vcc i pvcc i boost v cc = pv cc = boost = 5v tg, bg float tg, bg load (pf) 0 0 i pvcc , i boost (ma) 5 15 20 25 35 1704 g27 10 30 4000 10000 2000 6000 8000 t a = 25 c pv cc = boost = 5v
ltc1704/ltc1704b 8 1704bfa pi fu ctio s uuu compensation and soft-start connections should return to gnd. gnd and pgnd should connect only at a single point, near the pgnd pin and the negative plate of the v in bypass capacitor. regfb (pin 9): linear regulator controller feedback input. regfb should be connected through a resistor divider network to v outreg to set the output voltage of the linear regulator. regilm (pin 10): linear regulator controller current limit setting cum on/off control. this pin is internally servoed to 0.8v. an external resistor r regilm between v cc and regilm programs the regilm pin input current. this current determines the maximum pass transistor base current and directly controls the linear regulator current sourcing capabilitiy. an external capacitor, c delay is added to this pin to control the turn-on time of the linear regula- tor, the minimum value for this capacitor is 100pf. refer to the linear regulator current limit programming sec- tion for more information on choosing r regilm and c delay . pulling regilm to gnd turns off the linear regulator. if both run/ss and regilm are pulled low, the ltc1704 enters shutdown mode. v cc (pin 11): power supply input. all internal circuits except the switcher output drivers are powered from this pin. v cc should be connected to a low noise 5v supply, and should be bypassed to gnd with at least a 10 m f capacitor in close proximity to the ltc1704. pgood (pin 12): power good. pgood is an open-drain logic output. pgood pulls low if any of the two supply outputs are outside 10% of their nominal levels. an external pull-up resistor is required at pgood to allow it to swing positive. pgnd (pin 13): power ground. the bg driver returns to this pin. connect pgnd to a high current ground node in close proximity to the sources of external mosfet qb, and the v in and v outsw bypass capacitors. bg (pin 14): switcher controller bottom gate drive. the bg pin drives the gate of the bottom n-channel synchro- nous switch mosfet, qb. bg is designed to typically drive up to 10,000pf of gate capacitance. pv cc (pin 15): switcher controller bottom gate driver sup- ply. pv cc provides power to the bg output driver. pv cc must be connected to a voltage high enough to fully turn on the external mosfet, qb. pv cc should generally be con- nected directly to v in , the main system 5v supply. pv cc requires at least a 10 m f bypass capacitor directly to pgnd. boost (pin 16): switcher controller top gate driver supply. the boost pin supplies power to the floating tg driver. bypass boost to sw with a 1 m f capacitor. an external schottky diode from v in to boost creates a complete floating charge-pumped supply at boost. no other external supplies are required. test circuit tg sw i max run/ss comp fb regdr gnd boost pv cc bg pgnd pgood v cc regilm regfb 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc1704 2000pf 80k r regilm 100k 10 f 5v i boost + 100pf 1704 tc i pvcc i vcc 250k 100 v fb f osc 2k 1 f 2000pf
ltc1704/ltc1704b 9 1704bfa block diagra w pwrgd delay osc 550khz 0.720v 0.8v 0.8v power-up linear regulator regfb 0.880v soft- start burst and driver logic 0.720v 0.880v 0.760v 0.840v 0.800v mpg pwrbad reg pwrbad switcher 0.5v power down shutdown switcher driver 10 a max burst min ppgreg npgreg ppg npg sscmp pwm ilm i max boost pgood run/ss tg sw comp fb 1704 bd pv cc pgnd gnd v cc 3 a 15 11 4 12 8 13 6 5 2 bg pv cc 14 1 16 3 0.8v bandgap reference reg ilm 2ma regdr mreg 1.9 a 7 regfb 9 regilm mregilm amp fb 10 v b = 2v typ v a = 1v typ
ltc1704/ltc1704b 10 1704bfa overview the ltc1704 includes a step-down (buck), voltage mode feedback switching regulator controller and a linear regu- lator controller. the switching regulator controller em- ploys a synchronous switching architecture with two external n-channel mosfets. the chip operates from a low voltage input supply (6v maximum) and provides high power, high efficiency, precisely regulated output voltage. the switcher output regulation is extremely tight, with initial accuracy and dc line and load regulation and better than 1.5%. total regulation, including transient response, is inside of 3.5% with a properly designed circuit. the 550khz switching frequency allows the use of physically small, low value external components without compro- mising performance. the ltc1704s internal feedback amplifier is a 20mhz gain bandwidth op amp, allowing the use of complex multipole/ zero compensation networks. this allows the feedback loop to maintain acceptable phase margin at higher fre- quencies than traditional switching regulator controllers, improving stability and maximizing transient response. the 800mv internal reference allows regulated output voltages as low as 800mv without external level shifting amplifiers. the ltc1704s synchronous switching logic transitions automatically into burst mode operation, maxi- mizing efficiency with light loads. the linear regulator controller drives an external npn pass transistor to provide a programmable output voltage up to 2a of current. an external pull-up resistor programs the current limit threshold for the linear regulator. under short-circuit condition, the foldback current limit circuitry prevents excessive pass transistor heating. the switcher and the linear regulator can be individually disabled. when both controllers are disabled, the ltc1704 enters shut- down mode and the supply current reduces to 75 m a. an onboard power good (pgood) flag goes high when both outputs are regulating. small footprint the ltc1704 switcher supply operates at a 550khz switch- ing frequency, allowing it to use low value inductors without generating excessive ripple currents. because the inductor stores less energy per cycle, the physical size of the inductor can be reduced without risking core satura- tion, saving pcb board space. the high operating fre- quency also means less energy is stored in the output capacitors between cycles, minimizing their required value and size. the remaining components, including the ltc1704, are tiny, allowing an entire power convertor to be constructed in 1.5in 2 of pcb space. fast transient response the ltc1704 switcher supply uses a fast 20mhz gbw op amp as an error amplifier. this allows the compensation network to be designed with several poles and zeros in a more flexible configuration than with a typical g m feedback amplifier. the high bandwidth of the amplifier, coupled with the high switching frequency and the low values of the external inductor and output capacitor, allow very high loop crossover frequencies. the low inductor value is the other half of the equationwith a typical value on the order of 1 m h, the inductor allows very fast di/dt slew rates. the result is superior transient response compared with conventional solutions. high efficiency the ltc1704 switcher supply uses a synchronous step- down (buck) architecture, with two external n-channel mosfets. a floating topside driver and a simple external charge pump provide full gate drive to the upper mosfet. the voltage mode feedback loop and mosfet v ds current limit sensing remove the need for an external current sense resistor, eliminating an external component and a source of power loss in the high current path. properly designed circuits using low gate charge mosfets are capable of efficiencies exceeding 90% over a wide range of output voltages. linear regulator controller the ltc1704 linear regulator controller drives an exter- nal npn pass transistor in emitter-follower configuration to provide an externally adjustable output voltage. the con- troller senses the output voltage via the regfb pin, drives the base of the npn through the regdr pin to regulate the regfb pin to 0.8v. regdr is capable of sourcing more than 30ma of base current to the external npn. applicatio s i for atio wu u u
ltc1704/ltc1704b 11 1704bfa applicatio s i for atio wu u u overcurrent protection is achieved by limiting the drive current. the input current at the regilm pin programs the current limit threshold. refer to the linear regulator supply current limit programming section for more information on choosing r regilm . the linear regulator controller employs a foldback current limit scheme for overcurrent protection. under a short-circuit condition, the external npn transistor is subjected to the full input voltage across its collector-emitter terminal. this increases the power dissipation of the npn and may eventually cause damage to the transistor. ltc1704 overcomes this problem by using a foldback current limit scheme whereby the available drive current is reduced as the output voltage at regfb pin drops. this limits the power dissipation and prevents catastrophic damage to the external npn. architecture details switcher supply architecture the ltc1704 switcher supply is designed to operate as a synchronous buck converter (figure 1). the controller includes two high power mosfet gate drivers to control the external n-channel mosfets qt and qb. the drivers have 0.5 w output impedances and can carry over an amp of continuous current with peak currents up to 5a to slew large mosfet gates quickly. the drain of qt is connected to the input supply and the source of qt connected to the switching node sw. qb is the synchronous rectifier with its drain at sw and its source at pgnd. sw is connected to one end of the inductor, with the other end connected to v outsw . the output capacitor is connected from v outsw to pgnd. when a switching cycle begins, qb is turned off and qt is turned on. sw rises almost immediately to v in and the inductor current begins to increase. when the pwm pulse completes, qt turns off and one nonoverlap interval later, qb turns on. now sw drops to pgnd and the inductor current decreases. the cycle repeats with the next tick of the master clock. the percentage of time spent in each mode is controlled by the duty cycle of the pwm signal, which in turn is controlled by the feedback amplifier. the master clock runs at a 550khz rate and turns qt once every 1.8 m s. in a typical application with a 5v input and a 1.5v output, the duty cycle will be set at 1.5/5 ? 100% or 30% by the feedback loop. this will give roughly a 540ns on-time for qt and a 1.26 m s on-time for qb. this constant frequency operation brings with it a couple of benefits. inductor and capacitor values can be chosen with a precise operating frequency in mind and the feed- back loop components can be similarly tightly specified. noise generated by the circuit will always be in a known frequency band with the 550khz frequency designed to leave the 455khz if band free of interference. subharmonic oscillation and slope compensation, common headaches with constant frequency current mode switchers, are absent in voltage mode designs like the ltc1704. during the time that qt is on, its source (the sw pin) is at v in . v in is also the power supply for the ltc1704. however, qt requires v in + v gs(on) at its gate to achieve minimum r on . the ltc1704, needs to generate a gate drive signal at tg higher than its highest supply voltage. to accomplish this, the tg driver runs from floating supplies, with its negative supply attached to sw and its power supply at boost. this allows it to slew up and down with the source of qt. figure 1. synchronous buck architecture tg sw bg pgnd ltc1704 qt c in qb l + c outsw 1704 f01 v outsw v in + figure 2. floating tg driver supply tg c cp d cp boost sw bg pgnd pv cc ltc1704 qt c in qb l + c outsw 1704 f02 v outsw v in +
ltc1704/ltc1704b 12 1704bfa applicatio s i for atio wu u u in combination with a simple external charge pump (fig- ure 2), this allows the ltc1704 to completely enhance the gate of qt without requiring an additional, higher supply voltage. switcher supply feedback amplifier the ltc1704 senses the switcher output voltage at v outsw with an internal feedback op amp (see block diagram). this is a real op amp with a low impedance output, 85db open-loop gain and 20mhz gain bandwidth product. the positive input is connected internally to an 800mv refer- ence, while the negative input is connected to the fb pin. the output is connected to comp, which is in turn con- nected to the soft-start circuitry and from there to the pwm generator. the switching regulator output voltage can be obtained using the following equation: vv r r outsw =+ ? ? ? ? 08 1 1 2 . unlike many regulators that use a resistor divider con- nected to a high impedance feedback input, the ltc1704 switcher supply is designed to use an inverting summing amplifier topology with the fb pin configured as a virtual ground. this allows flexibility in choosing pole and zero locations not available with simple g m configurations. in particular, it allows the use of type 3 compensation, which provides a phase boost at the lc pole frequency and significantly improves loop phase margin (refer to figure 3). switcher supply min/max comparators two additional feedback loops in the switcher supply keep an eye on the primary feedback amplifier and step in if the feedback node moves 5% from its nominal 800mv value. the max comparator (see block diagram) activates when- ever fb rises more than 5% above 800mv. it immediately turns the top mosfet (qt) off and the bottom mosfet (qb) on and keeps them that way until fb falls back within 5% of its nominal value. this pulls the output down as fast as possible, preventing damage to the (often expensive) load. if fb rises because the output is shorted to a higher supply, qb will stay on until the short goes away, the higher supply current limits or qb dies trying to save the load. this behavior provides maximum protection against overvoltage faults at the output, while allowing the circuit to resume normal operation when the fault is removed. the min comparator (see block diagram) trips whenever fb is more than 5% below 800mv and immediately forces the switch duty cycle to 90% to bring the output voltage back into range. it releases when fb is within the 5% window. min is disabled when the soft-start or current limit circuits are activethe only two times that the output should legitimately be below its regulated value. notice that the fb pin is the virtual ground node of the feedback amplifier. a typical compensation network does not include local dc feedback around the amplifier, so that the dc level at fb will be an accurate replica of the output voltage, divided down by r1 and r2 (figure 3). however, the compensation capacitors will tend to attenuate ac signals at fb, especially with low bandwidth type 1 feed- back loops. this creates a situation where the min and max comparators do not respond immediately to shifts in the output voltage, since they monitor the output at fb. pgood flag the ltc1704 comes with a power good pin (pgood). pgood is an open-drain output, and requires an external pull-up resistor. if both the regulators are within 10% from their nominal value, the transistor mpg shuts off (see block diagram), and pgood is pulled high by the external pull-up resistor. if any of the two outputs is more than 10% outside the nominal value for more than 1 m s, pgood pulls figure 3. "type 3" feedback loop + fb 0.8v r1 fb v outsw ltc1704 comp 1704 f03 r3 c3 c2 r2 r4 c1
ltc1704/ltc1704b 13 1704bfa applicatio s i for atio wu u u low, indicating that the output is out of regulation. for pgood to go high, both the outputs must be in regulation for more than 20 m s. pgood remains active during soft- start and current limit. upon power-up, pgood is forced low. as soon as the run/ss and regilm pins rise above the shutdown thresholds, the two pairs of power good comparators take over and control the transistor mpg directly. the 1 m s and 20 m s delay ensures that short output transient glitches that are successfully caught by the power good comparators dont cause momentary glitches at the pgood pin. shutdown/soft-start the run/ss pin performs two functions: when pulled to ground, it shuts down the switcher drivers, and acts as a conventional soft-start pin, enforcing a maximum duty cycle limit proportional to the voltage at run/ss. an internal 3 m a current source pull-up is connected to the run/ss pin, allowing a soft-start ramp to be generated with a single external capacitor to ground. the 3 m a current source is active even when the ltc1704 is shut down, ensuring the device will start when any external pull-down at run/ss is released. the run/ss pin shuts down the switcher drivers when it falls below 0.5v (figure 4). between 0.5v and about 1v, the ltc1704 wakes up and the duty cycle is kept to minimum. as the potential at run/ss goes higher, the duty cycle increases linearly between 1v and 2v, reaching its final value of 90% when run/ss is above 2v. some- where before this point, the feedback amplifier will as- sume control of the loop and the output will come into regulation. when run/ss rises to 1v below v cc , the min feedback comparator is enabled, and the ltc1704 voltage feedback loop is in full operation. switcher supply current limit the ltc1704 switcher supply includes an onboard cur- rent limit circuit that limits the maximum output current to a user-programmed level. it works by sensing the voltage drop across qb during the time that qb is on and compar- ing that voltage to a user-programmed voltage at i max . since qb looks like a low value resistor during its on-time, the voltage drop across it is proportional to the current flowing in it. in a buck converter, the average current in the inductor is equal to the output current. this current also flows through qb during its on-time. thus, by watching the voltage across qb, the ltc1704 can monitor the output current. any time qb is on and the current flowing to the output is reasonably large, the sw node at the drain of qb will be somewhat negative with respect to pgnd. the ltc1704 senses this voltage and inverts it to allow it to compare the sensed voltage with a positive voltage at the i max pin. the i max pin includes a trimmed 10 m a pull-up, enabling the user to set the voltage at i max with a single resistor, r imax , to ground. the ltc1704 compares the two inputs and begins limiting the output current when the magnitude of the negative voltage at the sw pin is greater than the voltage at i max . the current limit detector is connected to an internal gm amplifier that pulls a current from the run/ss pin propor- tional to the difference in voltage magnitudes between the sw and i max pins. this current begins to discharge the soft-start capacitor at run/ss, reducing the duty cycle and controlling the output voltage until the current drops below the limit. the soft-start capacitor needs to move a fair amount before it has any effect on the duty cycle, adding a delay until the current limit takes effect (figure 4). this allows the ltc1704 to experience brief overload conditions without affecting the output voltage regulation. figure 4. soft-start operation in start up and current limit 0v v out 5v 4v 2v 1v 0.5v minimum duty cycle 0v 1704 f04 driver disable mode ltc1704 enable min comparator enable run/ss controls duty cycle comp controls duty cycle start-up normal operation current limit hard current limit
ltc1704/ltc1704b 14 1704bfa applicatio s i for atio wu u u the delay also acts as a pole in the current limit loop to enhance loop stability. prolonged overload conditions will allow the run/ss pin to reach a steady state, and the output will remain at a reduced voltage until the overload is removed. under current limit condition, if the output voltage is less than 10% of its normal value, the soft-start capacitor will be forced low immediately and the ltc1704 will rerun a complete soft-start cycle. the soft-start ca- pacitor must be selected such that during power-up the current through qb will not exceed the current limit value. power mosfet r ds(on) varies from mosfet to mosfet, limiting the accuracy obtainable from the ltc1704 current limit loop. additionally, ringing on the sw node due to parasitics can add to the apparent current, causing the loop to engage early. when the load current increases abruptly, the voltage feedback loop forces the duty cycle to increase rapidly and the on-time of qb will be small momentarily. the r ds(on) of qb must be low enough to ensure that the sw node is pulled low within the qb on- time for proper current sensing. the ltc1704 current limit is designed primarily as a disaster prevention, no blow- up circuit, and is not useful as a precision current regu- lator. it should typically be set around 50% above the maximum expected normal output current to prevent com- ponent tolerances from encroaching on the normal cur- rent range. see the switching supply current limit pro- gramming section for advice on choosing a valve for r imax . burst mode operation theory of operation the ltc1704 (non-b part) switcher supply has two modes of operation. under heavy loads, it operates as a fully synchronous, continuous conduction switching regula- tor. in this mode of operation (continuous mode), the current in the inductor flows in the positive direction (toward the output) during the entire switching cycle, constantly supplying current to the load. in this mode, the synchronous switch (qb) is on whenever qt is off, so the current always flows through a low impedance switch, minimizing voltage drop and power loss. this is the most efficient mode of operation at heavy loads, where the resistive losses in the power devices are the dominant loss term. continuous mode works efficiently when the load current is greater than half of the ripple current in the inductor. in a buck converter like the ltc1704, the average current in the inductor (averaged over one switching cycle) is equal to the load current. the ripple current is the difference between the maximum and the minimum current during a switching cycle (see figure 5a). the ripple current depends on inductor value, clock frequency and output voltage, but is constant regardless of load as long as the ltc1704 remains in continuous mode. see the inductor selection section for a detailed description of ripple current. as the output load current decreases in continuous mode, the average current in the inductor will reach a point where it drops below half the ripple current. at this point, the current in the inductor will reverse during a portion of the switching cycle, or begin to flow from the output back to the input. this does not adversely affect regulation, but does cause additional losses as a portion of the inductor current flows back and forth through the resistive power switches, giving away a little more power each time and lowering the efficiency. there are some benefits to allow- ing this reverse current flow: the circuit will maintain regulation even if the load current drops below zero (the load supplies current to the ltc1704) and the output ripple voltage and frequency remain constant at all loads, easing filtering requirements. besides the reverse current loss, the ltc1704 drivers are still switching qt and qb on and off once a cycle. each time an external mosfet is turned on, the internal driver must charge its gate to pv cc . each time it is turned off, that charge is lost to ground. at the high switching frequency that the ltc1704 operates, the charge lost to the gates can add up to tens of milliamps from pv cc . as the load current continues to drop, this quickly becomes the dominant power loss term, reducing efficiency once again. to minimize the efficiency loss due to switching loss and reverse current flow at light loads, the ltc1704 (non-b part) switches to a second mode of operation: burst mode operation (figure 5b). in burst mode operation, the ltc1704 detects when the inductor current approaches zero and turns off both drivers. during this time, the voltage at the sw pin will float around v outsw , the voltage (for non-b parts only)
ltc1704/ltc1704b 15 1704bfa applicatio s i for atio wu u u across the inductor will be zero, and the inductor current remains zero. this prevents current from flowing back- wards in qb, eliminating that power loss term. it also reduces the ripple current in the inductor as the output current approaches zero. the burst comparator is turned on only at the last 180ns of the switching period, the propagation delay of the comparator is designed to be fast so that a zero or low positive voltage on the sw node can trip the comparator within this 180ns. low inductor ripple current coupled with low mosfet r ds(on) may prolong the delay of the burst comparator and prevent the comparator from trip- ping. to overcome this, reduce the inductor value to increase the ripple current and the sw node voltage change. the moment ltc1704 (non-b parts) enters burst mode operation, both drivers skip several switching cycles until the output droops. once the voltage feedback loop requests for an additional 10% duty cycle, the ltc1704 enters con- tinuous mode operation again. to eliminate audible noise from certain types of inductors when they are lightly loaded, ltc1704 includes an internal timer that forces continuous mode operation every 15 m s. in burst mode operation, both resistive loss and switching loss are minimized while keeping the output in regulation. the total deviation from the regulated output is within the 1.5% regulation tolerance of the ltc1704. as the load current falls to zero in burst mode operation, the most significant loss term becomes the 4.5ma quiescent cur- rent drawn by the ltc1704usually much less than the minimum load current in a typical low voltage logic sys- tem. burst mode operation maximizes efficiency at low load currents, but can cause low frequency ripple in the output voltage as the cycle-skipping circuitry switches on and off. inductor current i ripple time i average i average inductor current i ripple time 1704 f05 the ltc1704b does not shift into burst mode operation at light loads, eliminating low frequency output ripple at the expense of light load efficiency. the ltc1704 detects when the inductor current has reached zero by monitoring the voltage at the sw pin while qb is on (see burst in block diagram). since qb acts like a resistor, sw should ideally be right at 0v when the inductor current reaches zero. in reality, the sw node will ring to some degree immediately after it is switched to ground by qb, causing some uncertainty as to the actual moment the average current in qb goes to zero. the ltc1704 minimizes this effect by turning on the burst comparator only at the last 180ns of the switching period, before qb turns off. in addition, the burst comparator is disabled if qb turns on for less than 200ns. despite this, care must still be taken in the pcb layout to ensure that proper kelvin sensing for the sw pin is provided. connect the sw pin of the ltc1704 as close to the drain of qb as possible through a thick trace. the same applies to the pgnd pin of the ltc1704, which is the negative input of the burst comparator and it should be connected close to the source of qb through a thick trace. ringing on the pgnd pin due to an insufficient pv cc bypass capacitor can also cause the burst comparator to trip prematurely. connect at least a 10 m f bypass capacitor directly from the pv cc pin to pgnd. burst comparator disabled if qb turns on for less than 200ns burst comparator turns on 180ns before qb turns off time v sw 0v 5v 0v v bg time 1704 f06 figure 6. burst comparator turns on 180ns before qb turns off figure 5a. continous mode figure 5b. burst mode operation
ltc1704/ltc1704b 16 1704bfa applicatio s i for atio wu u u maximizing high load current efficiency efficiency at high load currents is primarily controlled by the resistance of the components in the power path (qt, qb, l) and power lost in the gate drive circuits due to mosfet gate charge. maximizing efficiency in this region of operation is as simple as minimizing these terms. the behavior of the load over time affects the efficiency strategy. parasitic resistances in the mosfets and the inductor set the maximum output current the circuit can supply without burning up. a typical efficiency curve shows that peak efficiency occurs near 30% of this maxi- mum current. if the load current will vary around the efficiency peak and spend relatively little time at the maximum load, choosing components so that the average load is at the efficiency peak is a good idea. this puts the maximum load well beyond the efficiency peak, but usu- ally gives the greatest system efficiency over time, which translates to the longest run time in a battery-powered system. if the load is expected to be relatively constant at the maximum level, the components should be chosen so that this load lands at the peak efficiency point, well below the maximum possible output of the converter. maximizing low load current efficiency low load current efficiency depends strongly on proper operation in burst mode operation. in an ideally optimized system, when burst mode operation is activated, gate drive is the dominant loss term. burst mode operation turns off all output switching for several clock cycles in a row, significantly cutting gate drive losses. as the load current in burst mode operation falls toward zero, the current drawn by the circuit falls to the ltc1704s back- ground quiescent level, about 4.5ma. to maximize low load efficiency, make sure the ltc1704 (non-b part) is allowed to enter burst mode operation as cleanly as possible. minimize ringing at the sw node so that the burst comparator leaves as little residual current in the inductor as possible when qb turns off. it helps to connect the sw pin of the ltc1704 as close to the drain of qb as possible. an rc snubber network can also be added from sw to pgnd. switcher supply external component selection power mosfets selection getting peak efficiency out of the ltc1704 switcher sup- ply depends strongly on the external mosfets used. the ltc1704 requires at least two external mosfetsmore if one or more of the mosfets are paralleled to lower on- resistance. to work efficiently, these mosfets must exhibit low r ds(on) at 5v v gs to minimize resistive power loss while they are conducting current. they must also have low gate charge to minimize transition losses during switching. on the other hand, voltage breakdown require- ments in a typical ltc1704 circuit are pretty tame; the 6v maximum input voltage limits the v ds and v gs the mosfets can see to safe levels for most devices. low r ds(on) r ds(on) calculations are pretty straightforward. r ds(on) is the resistance from the drain to the source of the mosfet when the gate is fully on. many mosfets have r ds(on) specified at 4.5v gate drivethis is the right number to use in ltc1704 circuits running from a 5v supply. as current flows through this resistance while the mosfet is on, it generates i 2 r watts of heat, where i is the current flowing (usually equal to the output current) and r is the mosfet r ds(on) . this heat is only generated when the mosfet is on. when it is off, the current is zero and the power lost is also zero (and the other mosfet is busy losing power). this lost power does two things: it subtracts from the power available at the output, costing efficiency, and it makes the mosfet hotter, both bad things. the effect is worst at maximum load when the current in the mosfets and thus the power lost, are at a maximum. lowering r ds(on) improves heavy load efficiency at the expense of additional gate charge (usually) and more cost (usually). proper choice of mosfet r ds(on) becomes a trade-off between tolerable efficiency loss, power dissipation and cost. note that while the lost power has a significant effect on system efficiency, it only adds up to a watt or two in a typical ltc1704 circuit, allowing the use of small, surface mount mosfets without heat sinks.
ltc1704/ltc1704b 17 1704bfa applicatio s i for atio wu u u gate charge gate charge is amount of charge (essentially, the number of electrons) that the ltc1704 needs to put into the gate of an external mosfet to turn it on. the easiest way to visualize gate charge is to think of it as a capacitance from the gate pin of the mosfet to sw (for qt) or to pgnd (for qb). this capacitance is composed of mosfet channel charge, actual parasitic drain-source capacitance and miller-multiplied gate-drain capacitance, but can be ap- proximated as a single capacitance from gate to source. regardless of where the charge is going, the fact remains that it all has to come out of pv cc to turn the mosfet gate on, and when the mosfet is turned back off, that charge all ends up at ground. in the meanwhile, it travels through the ltc1704s gate drivers, heating them up. more power lost! in this case, the power is lost in little bite-sized chunks, one chunk per switch per cycle, with the size of the chunk set by the gate charge of the mosfet. every time the mosfet switches, another chunk is lost. clearly, the faster the clock runs, the more important gate charge becomes as a loss term. old fashioned switchers that ran at 20khz could pretty much ignore gate charge as a loss term. in the 550khz ltc1704, gate charge loss can be a significant efficiency penalty. gate charge loss can be the dominant loss term at medium load currents, especially with large mosfets. gate charge loss is also the primary cause of power dissipation in the ltc1704 itself. tg charge pump theres another nuance of mosfet drive that the ltc1704 needs to get around. the ltc1704 is designed to use n-channel mosfets for both qt and qb, primarily be- cause n-channel mosfets generally cost less and have lower r ds(on) than similar p-channel mosfets. turning qb on is no big deal since the source of qb is attached to pgnd; the ltc1704 just switches the bg pin between pgnd and pv cc . driving qt is another matter. the source of qt is connected to sw which rises to v in when qt is on. to keep qt on, the ltc1704 must get tg one mosfet v gs(on) above v in . it does this by utilizing a floating driver with the negative lead of the driver attached to sw (the source of qt) and the pv cc lead of the driver coming out separately at boost. an external 1 m f capacitor (c cp ) connected between sw and boost (figure 2) supplies power to boost when sw is high, and recharges itself through dcp when sw is low. this simple charge pump keeps the tg driver alive even as it swings well above v in . the value of the bootstrap capacitor c cp needs to be at least 100 times that of the total input capacitance of the topside mosfet(s). for very large external mosfets (or multiple mosfets in parallel), c cp may need to be in- creased beyond the 1 m f value. input supply the bicmos process that allows the ltc1704 switcher supply to include large mosfet drivers on-chip also limits the maximum input voltage to 6v. this limits the practical maximum input supply to a loosely regulated 5v or 6v rail. at the same time, the input supply needs to supply several amps of current without excessive voltage drop. the input supply must have regulation adequate to prevent sudden load changes from causing the ltc1704 input voltage to dip. in most typical applications where the ltc1704 is generating a secondary low voltage logic supply, all of these input conditions are met by the main system logic supply when fortified with an input bypass capacitor. input bypass capacitor selection a typical ltc1704 circuit running from a 5v logic supply might provide 1.6v at 10a at its switcher output. 5v to 1.6v implies a duty cycle of 32%, which means qt is on 32% of each switching cycle. during qts on-time, the current drawn from the input equals the load current and during the rest of the cycle, the current drawn from the input is near zero. this 0a to 10a, 32% duty cycle pulse train results in 4.66a rms ripple current. at 550khz, switch- ing cycles last about 1.8 m s; most system logic supplies have no hope of regulating output current with that kind of speed. a local input bypass capacitor is required to make up the difference and prevent the input supply from dropping drastically when qt kicks on. this capacitor is usually chosen for rms ripple current capability and esr as well as value. consider our 10a example. the input bypass capacitor gets exercised in three ways: its esr must be low enough
ltc1704/ltc1704b 18 1704bfa applicatio s i for atio wu u u to keep the initial drop as qt turns on within reason (100mv or so); its rms current capability must be ad- equate to withstand the 4.66a capacitor ripple current is not the same as input rms current at the input and the capacitance must be large enough to maintain the input voltage until the input supply can make up the difference. generally, a capacitor that meets the first two parameters will have far more capacitance than is required to keep capacitance-based droop under control. in our example, we need 0.01 w esr to keep the input drop under 100mv with a 10a current step and 5.65a rms ripple current capacity to avoid overheating the capacitor. these re- quirements can be met with multiple low esr tantalum or electrolytic capacitors in parallel, or with a large mono- lithic ceramic capacitor. i ia ia rmsin dcin ripp rms = = == 565 32 565 32 466 22 . . (. ) (.) . tantalum capacitors are a popular choice as input capaci- tors for ltc1704 applications, but they deserve a special caution here. generic tantalum capacitors have a destruc- tive failure mechanism when they are subjected to large rms currents (like those seen at the input of an ltc1704). at some random time after they are turned on, they can blow up for no apparent reason. the capacitor manufac- turers are aware of this and sell special surge tested tantalum capacitors specifically designed for use with switching regulators. when choosing a tantalum input capacitor, make sure that it is rated to carry the rms current that the ltc1704 will draw. if the data sheet doesnt give an rms current rating, chances are the capacitor isnt surge tested. dont use it! output bypass capacitor selection the output bypass capacitor has quite different require- ments from the input capacitor. the ripple current at the output of a buck regulator, like the ltc1704s switcher controller, is much lower than at the input because the inductor current is constantly flowing at the output when- ever the ltc1704 is operating in continuous mode. the primary concern at the output is capacitor esr. fast load current transitions at the output will appear as voltage across the esr of the output bypass capacitor until the feedback loop in the ltc1704 can change the inductor current to match the new load current value. this esr step at the output is often the single largest budget item in the load regulation calculation. as an example, our hypotheti- cal 1.6v, 10a switcher with a 0.01 w esr output capacitor would experience a 100mv step at the output with a 0a to 10a load stepa 6.3% output change! usually the solution is to parallel several capacitors at the output. for example, to keep the transient response inside of 3% with the previous design, wed need an output esr better than 0.0048 w . this can be met with three 0.014 w , 470 m f tantalum capacitors in parallel. inductor selection the inductor in a typical ltc1704 circuit is chosen prima- rily for value and saturation current. the inductor value sets the ripple current, which is commonly chosen at around 40% of the anticipated full load current. ripple current is set by: i tv l ripple on qb out = () () in our hypothetical 1.6v, 10a example, we?d set the ripple to 40% of 10a or 4a, and the inductor value would be: l tv i sv a h with t v v khz s on qb out ripple on qb == m =m =- ? ? ? ? =m () () () (. )(. ) . . /. 12 16 4 05 1 16 5 550 1 2 the inductor must not saturate at the expected peak current. in this case, if the current limit was set to 15a, the inductor should be rated to withstand 15a + 1/2i ripple , or 17a without saturating. feedback loop/compensation feedback loop types in a typical ltc1704 switcher circuit, the feedback loop consists of the modulator, the external inductor and output capacitor, and the feedback amplifier and its com-
ltc1704/ltc1704b 19 1704bfa applicatio s i for atio wu u u pensation network. all of these components affect loop behavior and need to be accounted for in the loop compen- sation. the modulator consists of the internal pwm gen- erator, the output mosfet drivers and the external mosfets themselves. from a feedback loop point of view, it looks like a linear voltage transfer function from comp to sw and has a gain roughly equal to the input voltage. it has fairly benign ac behavior at typical loop compensation frequencies with significant phase shift appearing at half the switching frequency. the external inductor/output capacitor combination makes a more significant contribution to loop behavior. these components cause a second order lc roll-off at the output, with the attendant 180 phase shift. this roll-off is what filters the pwm waveform, resulting in the desired dc output voltage, but the phase shift complicates the loop compensation if the gain is still higher than unity at the pole frequency. eventually (usually well above the lc pole frequency), the reactance of the output capacitor will approach its esr, and the roll-off due to the capacitor will stop, leaving 6db/octave and 90 of phase shift (figure 7). so far, the ac response of the loop is pretty well out of the users control. the modulator is a fundamental piece of the ltc1704 design, and the external l and c are usually chosen based on the regulation and load current require- ments without considering the ac loop response. the feedback amplifier, on the other hand, gives us a handle with which to adjust the ac response. the goal is to have 180 phase shift at dc (so the loop regulates) and some thing less than 360 phase shift at the point that the loop gain falls to 0db. the simplest strategy is to set up the feedback amplifier as an inverting integrator, with the 0db frequency lower than the lc pole (figure 8). this type 1 configuration is stable but transient response will be less than exceptional if the lc pole is at a low frequency. figure 9 shows an improved type 2 circuit that uses an additional pole-zero pair to temporarily remove 90 of phase shift. this allows the loop to remain stable with 90 more phase shift in the lc section, provided the loop reaches 0db gain near the center of the phase bump. type 2 loops work well in systems where the esr zero in the lc roll-off hap- pens close to the lc pole, limiting the total phase shift due to the lc. the additional phase compensation in the feed- back amplifier allows the 0db point to be at or above the lc pole frequency, improving loop bandwidth substantially over a simple type 1 loop. it has limited ability to compen- sate for lc combinations where low capacitor esr keeps the phase shift near 180 for an extended frequency range. ltc1704 circuits using conventional switching grade elec- trolytic output capacitors can often get acceptable phase margin with type 2 compensation. type 3 loops (figure 10), use two poles and two zeros to obtain a 180 phase boost in the middle of the frequency band. a properly designed type 3 circuit can maintain acceptable loop stability even when low output capacitor esr causes the lc section to approach 180 phase shift well above the initial lc roll-off. as with a type 2 circuit, the loop should cross through 0db in the middle of the phase bump to maximize phase margin. many ltc1704 circuits use low esr tantalum or os-con output capaci- tors need type 3 compensation to obtain acceptable phase margin with a high bandwidth feedback loop. figure 7. transfer function of buck modulator gain (db) 1704 f05 a v 0 phase 6db/oct ?2db/oct gain phase (deg) freq ?0 180 270 360 figure 8. type 1 schematic and transfer function gain (db) 1704 f06 0 phase 6db/oct gain phase (deg) freq ?0 180 270 360 r2 r1 fb c1 in comp + v ref
ltc1704/ltc1704b 20 1704bfa applicatio s i for atio wu u u feedback component selection selecting the r and c values for a typical type 2 or type 3 loop is a nontrivial task. the applications shown in this data sheet show typical values, optimized for the power components shown. they should give acceptable perfor- mance with similar power components, but can be way off if even one major power component is changed significantly. applications that require optimized tran- sient response will need to recalculate the compensation values specifically for the circuit in question. the under- lying mathematics are complex, but the component values can be calculated in a straightforward manner if we know the gain and phase of the modulator at the crossover frequency. modulator gain and phase can be measured directly from a breadboard, or can be simulated if the appropriate para- sitic values are known. measurement will give more accu- rate results, but simulation can often get close enough to give a working system. to measure the modulator gain and phase directly, wire up a breadboard with an ltc1704 and the actual mosfets, inductor, and input and output capaci- tors that the final design will use. this breadboard should use appropriate construction techniques for high speed analog circuitry: bypass capacitors located close to the ltc1704, no long wires connecting components, appro- priately sized ground returns, etc. wire the feedback am- plifier as a simple type 1 loop, with a 10k resistor from v outsw to fb and a 0.1 m f feedback capacitor from comp to fb. choose the bias resistor (r2) as required to set the desired output voltage. disconnect r2 from ground and connect it to a signal generator or to the source output of a network analyzer (figure 11) to inject a test signal into the loop. measure the gain and phase from the comp pin to the output node at the positive terminal of the output ca- pacitor. make sure the analyzers input is ac coupled so that the dc voltages present at both the comp and v outsw nodes dont corrupt the measurements or damage the analyzer. figure 11. modulator gain/phase measurement setup boost 1 f 0.1 f mbr0530t tg sw bg pgnd pv cc gnd v cc 10 ac source from analyzer ltc1704 10 f qb l + c out 1704 f11 v outsw to analyzer v comp to analyzer r2 5v + run/ss nc qt fb comp 10k figure 9. type 2 schematic and transfer function figure 10. type 3 schematic and transfer function gain (db) 1704 f10 0 phase 6db/oct +6db/oct 6db/oct gain phase (deg) freq ?0 180 270 360 r2 v ref r1 r4 fb c2 in comp + c1 c3 r3 gain (db) 1704 f09 0 phase 6db/oct 6db/oct gain phase (deg) freq ?0 180 270 360 r2 v ref r1 r4 fb c2 in comp + c1 if breadboard measurement is not practical, a spice simulation can be used to generate approximate gain/ phase curves. plug the expected capacitor, inductor and mosfet values into the following spice deck and gener- ate an ac plot of v(v outsw )/v(comp) in db and phase of v(outsw) in degrees. refer to your spice manual for details of how to generate this plot.
ltc1704/ltc1704b 21 1704bfa applicatio s i for atio wu u u *1704 modulator gain/phase *2001 linear technology *this file written to run with pspice 9.0 *may require modifications for other spice simulators *mosfets rfet mod sw 0.02 ;mosfet rdson *inductor lext sw out1 1u ;inductor value rl out1 outsw 0.005 ;inductor series r *output cap cout outsw out2 1000u ;capacitor value resr out2 0 0.01 ;capacitor esr *1704 internals emod mod 0 comp 0 5 ;3.3 for 3.3v supply vstim comp 0 0 ac 1 ;ac stimulus .ac dec 100 1k 1meg .probe .end with the gain/phase plot in hand, a loop crossover fre- quency can be chosen. usually the curves look something like figure 7. choose the crossover frequency in the rising or flat parts of the phase curve, beyond the external lc poles. frequencies between 10khz and 50khz usually work well. note the gain (gain, in db) and phase (phase, in degrees) at this point. the desired feedback amplifier gain will be C gain to make the loop gain at 0db at this frequency. now calculate the needed phase boost, assum- ing 60 as a target phase margin: boost = C (phase + 30 ) if the required boost is less than 60 , a type 2 loop can be used successfully, saving two external components. boost values greater than 60 usually require type 3 loops for satisfactory performance. finally, choose a convenient resistor value for r1 (10k is usually a good value). now calculate the remaining values: (k is a constant used in the calculations) f = chosen crossover frequency g = 10 (gain/20) (this converts gain in db to g in absolute gain) type 2 loop: k tan boost c fgkr cck r k fc r vr vv ref outsw ref =+ ? ? ? ? = =- () = = - 2 45 2 1 21 12 1 4 21 2 1 2 p p () type 3 loop: k tan boost c fgr cck r k fc r r k c fkr r vr vv ref outsw ref =+ ? ? ? ? = =- () = = - = = - 2 4 45 2 1 21 12 1 4 21 3 1 1 3 1 23 2 1 p p p () switching supply current limit programming programming the current limit on the ltc1704 switcher supply is straightforward. the i max pin sets the current limit by setting the maximum allowable voltage drop across qb (the bottom mosfet) before the current limit circuit engages. the voltage across qb is set by its on- resistance and the current flowing in the inductor, which
ltc1704/ltc1704b 22 1704bfa applicatio s i for atio wu u u is the same as the output current. the ltc1704 current limit circuit inverts the voltage at i max before comparing it with the negative voltage across qb, allowing the current limit to be set with a positive voltage. to set the current limit, calculate the expected voltage drop across qb at the maximum desired current: v prog = (i limit )(r ds(on) ) i limit should be chosen to be quite a bit higher than the expected operating current, to allow for mosfet r ds(on) changes with temperature. setting i limit to 150% of the maximum normal operating current is usually safe and will adequately protect the power components if they are chosen properly. note that the ringing on the switch node can cause error for the current limit threshold (illustrated in figure 6). this factor will change depending on the layout and the components used. v prog is then pro- grammed at the i max pin using the internal 10 m a pull-up and an external resistor: r imax = v prog /10 m a the resulting value of r imax should be checked in an ac- tual circuit to ensure that the current circuit kicks in as expected. mosfet r ds(on) specs are like horsepower ratings in automobiles, and should be taken with a grain of salt. circuits that use very low values for r imax (< 10k) should be checked carefully, since small changes in r imax can cause large i limit changes when the switch node ring- ing makes up a large percentage of the total v prog value. if v prog is set too low, the ltc1704 may fail to start up. accuracy trade-offs the v ds sensing scheme used in the ltc1704 is not particularly accurate, primarily due to uncertainty in the r ds(on) from mosfet to mosfet. a second error term arises from the ringing present at the sw pin, which causes the v ds to look larger than (i load )(r ds(on) ) at the beginning of qbs on-time. another important error is due to poor pcb layout. care should be taken to ensure that proper kelvin sensing of the sw pin is provided. these inaccuracies do not prevent the ltc1704 current limit circuit from protecting itself and the load from damaging overcurrent conditions, but they do prevent the user from setting the current limit to a tight tolerance if more than one copy of the circuit is being built. the 50% factor in the current setting equation above reflects the margin neces- sary to ensure that the circuit will stay out of current limit at the maximum normal load, even with a hot mosfet that is running quite a bit higher than its r ds(on) spec. regulation over component tolerance/temperature dc regulation accuracy the ltc1704s switcher controller initial dc output accu- racy depends mainly on internal reference accuracy and internal op amp offset. two ltc1704 specs come into play: feedback voltage and feedback voltage line regula- tion. the feedback voltage spec is 800mv 12mv over the full temperature range and is specified at the fb pin, which encompasses both reference accuracy and any op amp offset. this accounts for 1.5% error at the output with a 5v input supply. the feedback voltage line regulation spec adds an additional 0.1%/v term that accounts for change in reference output with change in input supply voltage. with a 5v supply, the errors contributed by the ltc1704 itself add up to no more than 1.5% dc error at the output. the output voltage setting resistors (see r1 and r2 in the typical applications) are the other major contributor to dc error. at a typical 1.xv output voltage, the resistors are of roughly the same value, which tends to halve their error terms, improving accuracy. still, using 1% resistors for r1 and r2 will add 1% to the total output error budget. using 0.1% resistors in just those two positions can nearly halve the dc output error for very little additional cost. load regulation load regulation is affected by feedback voltage, feedback amplifier gain and external ground drops in the feedback path. feedback voltage is covered above and is within 1.5% over temperature. a full range load step might require a 10% duty cycle change to keep the output constant, requiring the comp pin to move about 100mv. with amplifier gain at 85db, this adds up to only a 10 m v shift at fb, negligible compared to the reference accuracy terms.
ltc1704/ltc1704b 23 1704bfa applicatio s i for atio wu u u external ground drops arent so negligible. the ltc1704 can sense the positive end of the output voltage by attaching the feedback resistor directly at the load, but it cannot do the same with the ground lead. just 0.001 w of resistance in the ground lead at 10a load will cause a 10mv error in the output voltageas much as all the other dc errors put together. proper layout becomes essential to achieving optimum load regulation from the ltc1704. a properly laid out ltc1704 circuit should move less than a millivolt at the output from zero to full load. transient response transient response is the other half of the regulation equation. the ltc1704 can keep the dc output voltage constant to within 1% when averaged over hundreds of cycles. over just a few cycles, however, the external components conspire to limit the speed that the output can move. consider a typical 5v to 1.5v circuit, subjected to a 1a to 5a load transient. initially, the loop is in regulation and the dc current in the output capacitor is zero. suddenly, an extra 4a start flowing out of the output capacitor while the inductor is still supplying only 1a. this sudden change will generate a (4a)(r esr ) voltage step at the output; with a typical 0.015 w output capacitor esr, this is a 60mv step at the output, or 4% (for a 1.5v output voltage.) very quickly, the feedback loop will realize that something has changed and will move at the bandwidth allowed by the external compensation network towards a new duty cycle. if the bandwidth is set to 50khz, the comp pin will get to 60% of the way to 90% duty cycle in 3 m s. now the inductor is seeing 3.5v across itself for a large portion of the cycle, and its current will increase from 1a at a rate set by di/dt = v/l. if the inductor value is 0.5 m h, the di/dt will be 3.5v/0.5 m h or 7a/ m s. sometime in the next few micro- seconds after the switch cycle begins, the inductor current will have risen to the 5a level of the load current and the output voltage will stop dropping. at this point, the induc- tor current will rise somewhat above the level of the output current to replenish the charge lost from the output capacitor during the load transient. during the next couple of cycles, the min comparator may trip on and off, preventing the output from falling below its C 5% thresh- old until the time constant of the compensation loop runs out and the main feedback amplifier regains control. with a properly compensated loop, the entire recovery time will be inside of 10 m s. most loads care only about the maximum deviation from ideal, which occurs somewhere in the first two cycles after the load step hits. during this time, the output capacitor does all the work until the inductor and control loop regain control. the initial drop (or rise if the load steps down) is entirely controlled by the esr of the capacitor and amounts to most of the total voltage drop. to minimize this drop, reduce the esr as much as possible by choosing low esr capacitors and/or paralleling multiple capacitors at the output. the capacitance value accounts for the rest of the voltage drop until the inductor current rises. with most output capacitors, several devices paralleled to get the esr down will have so much capacitance that this drop term is negligible. ceramic capacitors are an exception; a small ceramic capacitor can have suitably low esr with relatively small values of capacitance, making this second drop term significant. optimizing loop compensation loop compensation has a fundamental impact on tran- sient recovery time, the time it takes the ltc1704 to recover after the output voltage has dropped due to output capacitor esr. optimizing loop compensation entails maintaining the highest possible loop bandwidth while ensuring loop stability. the feedback component selec- tion section describes in detail the techniques used to design an optimized type 3 feedback loop, appropriate for most ltc1704 systems. measurement techniques measuring transient response presents a challenge in two respects: obtaining an accurate measurement and gener- ating a suitable transient to use to test the circuit. output measurements should be taken with a scope probe di- rectly across the output capacitor. proper high frequency probing techniques should be used. in particular, dont use the 6" ground lead that comes with the probe! use an adapter that fits on the tip of the probe and has a short ground clip to ensure that inductance in the ground path
ltc1704/ltc1704b 24 1704bfa applicatio s i for atio wu u u doesnt cause a bigger spike than the transient signal being measured. conveniently, the typical probe tip ground clip is spaced just right to span the leads of a typical output capacitor. make sure the bandwidth limit on the scope is turned off, since a significant portion of the transient energy occurs above the 20mhz cutoff. now that we know how to measure the signal, we need to have something to measure. the ideal situation is to use the actual load for the test, and switch it on and off while watching the output. if this isnt convenient, a current step generator is needed. this generator needs to be able to turn on and off in nanoseconds to simulate a typical switching logic load, so stray inductance and long clip leads between the ltc1704 and the transient generator must be minimized. figure 12 shows an example of a simple transient genera- tor. be sure to use a noninductive resistor as the load elementmany power resistors use an inductive spiral pattern and are not suitable for use here. a simple solution is to take ten 1/4w film resistors and wire them in parallel to get the desired value. this gives a noninductive resistive load which can dissipate 2.5w continuously or 50w if pulsed with a 5% duty cycle, enough for most ltc1704 circuits. solder the mosfet and the resistor(s) as close to the output of the ltc1704 circuit as possible and set up the signal generator to pulse at a 100hz rate with a 5% duty cycle. this pulses the ltc1704 with 500 m s transients 10ms apart, adequate for viewing the entire transient recovery time for both positive and negative transitions while keeping the load resistor cool. linear regulator supply linear regulator output voltage the linear regulator senses the output voltage at v outreg with an internal amplifier (see figure 13). the amplifier negative input is connected internally to an 800mv refer- ence, while the positive input is connected to the regfb pin. the amplifier output drives a p-channel transistor mreg, which is in turn connected to the external npn pass transistor. the linear regulator output voltage can be obtained using the following equation: vv r r outreg =+ ? ? ? ? 08 1 5 6 . figure 12. transient load generator ltc1704 v outsw irfz44 or equivalent r load 50 0v to 10v 100hz, 5% duty cycle locate close to the output 1704 f12 pulse generator figure 13. linear regulator qext moff r5 r6 regdr regilm mreg v cc v ref 2ma regfb 1704 f13 + c outreg v outreg v regon r regilm c delay i p v inreg regoff v cc 1.9 a ltc1704 reg ilm + regfb + amp linear regulator supplies requirement the linear regulator operates with two supplies: v cc for the ltc1704 and v inreg for the external npn transistor qext. both supplies must be higher than the minimum value determined by the linear regulator output voltage, v outreg . for a desired v outreg , use the following formula to calculate the minimum required v cc : minimum v cc = v outreg + v be(qext) + v dropout
ltc1704/ltc1704b 25 1704bfa where v be(qext) is base emitter voltage of qext and v dropout is the ltc1704 linear regulator controller drop- out voltage. the mjd44h11 from on semiconductor has a v be of around 0.9v at i c = 2a, 25 c and the ltc1704s v dropout is 1.1v maximum with 30ma of drive current. if the computed minimum v cc is less than the ltc1704 requirement of 3.15v then 3.15v should be used. the minimum v inreg is determined by the v ce saturation voltage of qext when it is driven with a base current equal to the maximum regdr pin drive current. the d44h11 has a saturation voltage of around 0.2v at i c = 2a, 25 c. a typical 1.5v v outreg , 2a application will need a mini- mum v cc of 1.5v + 0.9v + 1.1v = 3.5v and a minimum v inreg of 1.5v + 0.2v = 1.7v to operate. if a v outreg of 0.8v is needed, the minimum v cc should be 3.15v and the minimum v inreg is 0.8v + 0.2v = 1v. external npn pass transistor the external npn pass transistor for the ltc1704 linear regulator supply should be selected based on the follow- ing criteria: 1. maximum output current 2. dc current gain h fe 3. total allowable power dissipation 4. gain bandwidth product f t the npn transistor must be able to supply the maximum operating current for the linear regulator supply. at the same time, the dc current gain h fe must be large enough such that the pass transistor can supply the maximum load current with 30ma of base current. the transistor must not be subjected to power dissipation higher than the rated value, both during normal operation and over- load conditions. heat sink can be used to increase the alloweable power dissipation rating. the gain bandwidth product f t of the transistor determines how fast the linear regulator can follow an output load change without losing voltage regulation. the mjd44h11 from on semiconductor and sgs- thomson can be used in the ltc1704 linear regulator supply with current ratings up to 2a. the mjd44h11 from on semiconductor can supply 8a of output current and the minimum dc current gain h fe is 60 at ic = 2a. the power dissipation rating is 1.75w without heat sink and the gain bandwidth product f t of the mjd44h11 is typi- cally 50mhz. linear regulator supply current limit programming the ltc1704 linear regulator uses an external resistor r regilm to program the npn pass transistor base current. this indirectly programs the linear regulator current limit threshold. figure 13 shows the setup. one end of the resistor r regilm is connected to an external voltage source v regon or, alternatively, it can be connected to the v cc pin. the other end of the resistor is connected to the regilm pin. regilm is internally regulated to 0.8v. the voltage difference across this resistor generates the regilm pin input current. this current, together with the internal 1.9 m a current source, programs the regdr maxi- mum output current. the actual linear regulator current limit depends on the pass transistors widely distributed dc current gain h fe , which makes this current limit scheme not particularly accurate. nevertheless, this method re- moves the expensive current sense resistor and with careful design, it is sufficient to protect the external npn from over damaging. the following equation shows the relationship between r regilm and the linear regulator current limit threshold i lt : r v i h ma regilm regon lt fe = ()() ? ? ? ? . . 0 8 2100 75 where v regon is the pull-up voltage source for r regilm (see figure 13). when there is an overload at the linear regulator output, the current limit circuit fires and the output voltage drops. to protect the npn from excessive heating, the controller applicatio s i for atio wu u u
ltc1704/ltc1704b 26 1704bfa reduces the available base current to minimize the i load ? v ce product across the pass transistor. the amount of current reduction depends on the regfb pin voltage and the r regilm resistance (refer to the typical performance characteristics curves). this current limit foldback scheme limits the npn power dissipation and prevents it from blowing up. however, in cases when there is a constant current load at the regulator output, this current limit foldback scheme can create a start-up problem. in spite of this, most applications do not have full load requirement during start-up. to fulfill majority applications require- ments, the ltc1704 linear regulator allows a small amount of base current when the linear regulator output is shorted or v regfb = 0v. the actual regulator short-circuit current can be calculated from the following equation: ih ma v r sh fe regon regilm =+ ? ? ? ? 48 08 300 . . this short-circuit current should be checked against the load requirement to allow proper start-up. linear regulator power down the linear regulator can be powered down easily. a pull- down device (moff as shown in figure 13) that is capable of overcoming the regilm pin 1.9 m a weak pull-up current can shut down the linear regulator. as shown in figure 13, if the resistor r regilm is smaller than 400k, forcing v regon to ground can overcome the pull-up current and power down the linear regulator. when both the regilm and run/ss pins are forced low, ltc1704 enters shut- down mode and the quiescent current is reduced to 75 m a. linear regulator turn-on delay the external capacitor c delay from the regilm pin to ground allows the regilm pin to ramp up slowly and adds applicatio s i for atio wu u u a delay to the turn-on time of the linear regulator. the current through the resistor r regilm , the internal pull-up current and the external capacitor c delay controls the regilm pin slew rate. to power up the linear regulator, the potential at the regilm pin should not be below 0.8v. to add power sequencing to the linear regulator is easy. once the current limit resistor r regilm is chosen, the capacitor c delay can be added to program the turn on delay using the following equation: t c v r a delay delay regon regilm = +m 08 08 19 . . . the actual turn-on delay, which includes the time for the external npn to charge the output capacitor, will be longer than the calculated value. the ltc1704 linear regulator turn-on delay circuit is versatile; c delay capacitance should be larger than 100pf to allow instantaneous power up to seconds long delay. linear regulator output bypass capacitor the linear regulator requires the use of an output capacitor as part of the frequency compensation network. a mini- mum output capacitor of 10 m f with an esr lower than 100m w is recommended to prevent oscillations. larger values of output capacitance with low esr should be used to provide improved transient response for large load current changes. many different types of capacitors are available and have widely varying characteristics. these capacitors differ in capacitor tolerance (sometimes ranging up to 100%), equivalent series resistance, equivalent series inductance and capacitance temperature coefficient. low esr tanta- lum capacitors are recommended for this linear regulator.
ltc1704/ltc1704b 27 1704bfa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u package descriptio gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0502 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .053 ?.068 (1.351 ?1.727) .008 ?.012 (0.203 ?0.305) .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 typ .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
ltc1704/ltc1704b 28 1704bfa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2001 lt/tp 0303 1k rev a ? printed in usa related parts typical applicatio u part number description comments ltc1530 high power synchronous step-down controller so-8 with current limit, no r sense tm required ltc1628 dual high efficiency 2-pass synchronous step-down controller constant frequency, standby 5v and 3.3v ldos, 3.5v v in 36v ltc1699 smbus vid voltage programmers smbus interface, intel 5-bit mobile, intel desktop vid codes vrm8.4 and vrm9.0 ltc1703 dual 550khz synchronous 2-phase switching regulator vid control with 25mhz gbw voltage mode, v in 7v controller with vid ltc1705 dual 550khz synchronous switching regulator controller vid control with 20mhz gbw voltage mode, v in 6v with 5-bit vid plus ldo ltc1706-81 5-bit desktop vid programmer parallel interface, 0.8v reference intel desktop vid codes (vrm8.4) ltc1706-82 vid programmer for intel vrm9.0 parallel interface, 0.8v reference intel desktop vid codes (vrm9.0) ltc1736 synchronous step-down controller with 5-bit vid control output fault protection, power good output, 3.5v to 36v input ltc1778 no r sense current mode synchronous step-down controller up to 97% efficiency, 4v v in 36v, 0.8v v out (0.9)(v in ), i out up to 20a ltc3701 2-phase, low v in , dual step-down controller 2.5v v in 9.8v, 550khz operation, minimum c in , 16-lead ssop package no r sense is a trademark of linear technology corporation. vid controlled power supply + boost tg sw pgood regilm c cp 1 f 10 r max 13.7k r4 11k r3 1.8k v in 6 5 9 10 c3 1800pf 5k r regilm 470k 10 f + 10 f d cp mbr0520lt1 16 1 2 qtb 1 f l1 0.68 h 15 11 12 10 c ss 0.1 f c delay 1000pf qext on semiconductor d44h11 r5 1.69k r6 806 run/ss 4 gnd 8 regdr 7 regfb 9 1704 ta02 pv cc ltc1704 v cc qta bg 14 i max 3 pgnd 13 comp 5 fb 6 qba qbb + c outreg 100 f tant v outreg 2.5v 2a 3.3v 1 f c2 330pf c in : kemet t510x337k010as c outsw : panasonic eefue0g181r l1: sumida cep125-4712-t007 qta, qtb, qba, qbb: fairchild fds6670a c1 1800pf + + c outsw 180 f 4v 6 c in 330 f 10v 3 v in 5v v outsw 1.3v to 3.5v 15a fb v cc gnd vid4 vid3 vid2 sense ltc1706-81 from p vid1 vid0

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